Copper Electroplating for IC Substrates

Redistribution layers in IC substrate manufacturing require metallization of fine structures such as blind microvias, X-vias, and fine lines and pads. Systek UVF Series allows 2-in-1 RDL plating of these features in a single bath. The precise chemical system fills blind microvias and X-vias with minimal dimples or overfill, eliminating concerns of dielectric thinning and providing an excellent base for stacking. At the same time, the process also plates lines, pads, and other surface features with high coplanarity and low trace profiles.

Systek ETS 1200 is an advanced DC acid copper pattern plating process specifically formulated to plate fine lines and pads in embedded trace substrates and redistribution layers. The Systek ETS 1200 process excels at plating the trace profile tolerances and coplanarity requirements of die to IC substrate interfaces allowing R-values below 2 µm for lines and spaces as low as 5/5 µm. The deposit exceeds IPC Class III standards.

Systek MV 400 is a DC acid copper pattern plating process specifically designed for 2 in 1 RDL applications. Systek MV 400 consistently fills vias without voids and plates surface features like traces and pads with excellent coplanarity in a single step at high current densities. The production proven 3 component system is fully CVS analyzable.

Systek THF Series is a copper through hole filling process that enables improved thermal and structural designs for IC substrates. Systek THF Series provides a solid copper filled through hole in core PCB layers that has higher thermal conductivity than paste without thermal expansion commonly encountered with other materials. The process can fill through holes in a fraction of the time that would be required by direct current plating with minimal dimple and no need for surface planarization, simplifying the addition of subsequent build-up layers.