Optimize via step coverage, yield, and reliability for power/RF with our solutions that integrate seamlessly with die attach material.
Our range of solutions for backside metallization on power Integrated Circuits (ICs) and Radio Frequency (RF) devices enhances thermal conductivity and mechanical strength of thinned wafers. For devices containing vias, superior step coverage properties minimize the cost of precious metal content in each device.
We are here to help you. Please feel free to contact us with questions, comments or feedback.
Achieve superior bondability, reliability and thermal stability of display driver applications with our high-hardness gold solutions.
Learn MoreDesign next-generation Fan-Out Wafer Level Packaging (FOWLP) with our advanced gold and palladium solutions for thin metal films.
Learn MoreEnsure precise, uniform gold seed removal on TiW barriers with advanced, cost-effective gold etchants for semiconductor fabrication.
Learn MoreEnable high plating rates and superior step coverage with our advanced, cost-effective solutions for MEMS fabrication.
Learn MoreEnhance solderability and conductivity with high-purity deposits, seed filling, and adjustable roughness for advanced semiconductors.
Learn MoreIntegrated Solutions
Our complete range of pre-plate, strike, and plating solutions ensures superior results for compound semiconductor applications.
Sustainability
Our products minimize material usage for each die or wafer.
Reliability
We offer enabling materials that deliver consistent, high-quality characteristics.
Backside metallization is a process where metal layers are applied to the backside of a semiconductor wafer. These layers improve thermal management, mechanical strength, and electrical performance. The properties are essential for high-power, high-frequency devices in SiC, GaN and GaAs applications.
SiC, GaN and GaAs devices are costly substrates, and require high thermal conductivity and mechanical stability for device performance requirements. Backside metallization enables these properties while also enhancing reliability. Improving heat dissipation and interconnect efficiency of each die is critical for high-power IC's & RF applications.
Backside metallization is designed specifically to facilitate efficient heat transfer away from the die and into a heat spreading substrate. This is crucial for SiC, GaN and GaAs applications, which generate significant heat during operation. Successful backside metal stacks will improve device performance and longevity.
Common electroplated materials for backside metallization include gold, silver and palladium, as seen in our solutions including MICROFAB® AU660, NOVAFAB® AG-340, and NOVAFAB® PD ACID STRIKE. Electroless processes such as ENIG or ENEPIG are also commonly used for backside metallization. These various metal stack combinations can be tailored for requirements, delivering high thermal conductivity, excellent step coverage, and integration with sintered die attach materials.
Compound semiconductor devices have precisely engineered epitaxial layers that have very constrained temperature limits. Backside metallization enhances the device yield by improving heat dissipation properties required for minimizing device operating temperatures. High-quality metallization will result in reduced device failures on costly SiC, GaN and GaAs semiconductor devices.
